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MDT10C23
1. General Description
This ROM-Based 8 -bit micro-controller uses a fully static CMOS design technology to achieve high speed, small size, low power and high noise immunity. On chip memory includes 2K words ROM and80 bytes static RAM. Four comparator inputs with external Vref (not for 18 pin package) are also provided. u u u XTALStandard crystal oscillator HFXTHigh frequency crystal oscillator 4 oscillator start-up time can be selected by programming option: 150 s, 20 ms, 40 ms, 80 ms On-chip RC oscillator based Watchdog Timer(WDT) can be operated freely 12 I/O(for 18 pins package),14 I/O(for 20 pins package),16 I/O(for 22/24 pins package) pins with their own independent direction control
2. Features
u u u u Fully CMOS static design 8-bit data bus On chip ROM size : 2 K words Internal RAM size : 80 bytes (72 general purpose registers, 8 special registers) u u u u u u 36 single word instructions 14-bit instructions 2-level stacks Operating voltage : 2.3V ~ 5.5 V Operating frequency : 0 ~ 20 MHz The most fast execution time is 200 ns under 20 MHz in all single cycle instructions except the branch instruction u Addressing modes include direct, indirect and relative addressing modes u u u u u Built-in Power-on Reset 4 Channel comparator Power edge-detector Reset Sleep Mode for power saving 8-bit real time clock/counter(RTCC) with 8-bit programmable prescaler u 4 types of oscillator can be selected by programming option: RCLow cost RC oscillator LFXTLow frequency crystal oscillator
3. Applications
The application areas of this MDT10C23 range from appliance motor control and high speed automotive to low power remote transmitters/receivers, pointing devices, and telecommunications processors, such as Remote controller, small instruments, chargers, toy, automobile and PC peripheral ... etc
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 1
2004/7
Ver. 1.1
MDT10C23
4. Pin Assignment A1G20PINS, A2G22PINS, A3G24PINS, A5 :18 PINS PPDIP,SSOP, KSKINNY A1P,A1S A3S PA5 PA2/CIC2 PA3/CIC3 RTCC /MCLR Vss PB0 PB1 PB2 PB3 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 PA4/VREF PA1/CIC1 PA0/CIC0 OSC1 OSC2 Vdd PB7 PB6 PB5 PB4 NC PA7 PA5 PA2/CIC2 PA3/CIC3 RTCC /MCLR Vss PB0 PB1 PB2 PB3 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 NC PA6 PA4/VREF PA1/CIC1 PA0/CIC0 OSC1 OSC2 Vdd PB7 PB6 PB5 PB4
A2K PA7 PA5 PA2/CIC2 PA3/CIC3 RTCC /MCLR Vss PB0 PB1 PB2 PB3 1 2 3 4 5 6 7 8 9 10 11 22 21 20 19 18 17 16 15 14 13 12 PA6 PA4/VREF PA1/CIC1 PA0/CIC0 OSC1 OSC2 Vdd PB7 PB6 PB5 PB4 A5P,A5S PA2CIC2 1 PA3/CIC3 2 RTCC 3 /MCLR 4 Vss 5 PB0 6 PB1 7 PB2 8 PB3 9 18 17 16 15 14 13 12 11 10 PA1/CIC1 PA0/CIC0 OSC1 OSC2 Vdd PB7 PB6 PB5 PB4
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 2
2004/7
Ver. 1.1
MDT10C23
5. Block Diagram
Stack Two Levels
ROM 2KN14 (MDT10C23)
RAM 72N8 Port B
Port PB0 ~P B7 8 bits
11 bits 11 bits 14 bits
Program Counters
Instruction Register
Special Register
OS OS C1 C2 MC LR Instruction Decoder
D0~D 7 Port A
Oscillator Circuit
Control Circuit
Port PA 0~P A7 (22,24 pins) PA0~P A5 (20 pins) PA0~P A3 (18 pins) 8 bits
CMR0~C MR5 Comparat or mode Register
Power on Reset Power Down Reset Working Register ALU
Data 8-bit
Status Register
8-bit Timer/Counter
Prescale
WDT/OST Timer
RTCC
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 3
2004/7
Ver. 1.1
MDT10C23
6. Pin Function Description
Pin Name PA0~PA7 I/O I/O Function Description PA0~PA3 : TTL input level or comparator input PA4 : TTL input level or comparator VREF input PA5~PA7 : TTL input level PB0~PB7 RTCC /MCLR OSC1 OSC2 Vdd Vss NC I/O I I I O Port B, TTL input level Real Time Clock/Counter, Schmitt Trigger input levels Master Clear, Schmitt Trigger input levels Oscillator Input Oscillator Output Power supply Ground Unused ,do not connect
7. Memory Map
(A) Register Map
Address 00 01 02 03 04 05 06 07 08~0F 10~1F 30~3F 50~5F 70~7F
Description Indirect Addressing Register RTCC PC STATUS MSR Port A Port B Control register for comparator Internal RAM, General Purpose Register Internal RAM, Memory bank 0 Internal RAM, Memory bank 1 Internal RAM, Memory bank 2 Internal RAM, memory bank 3
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 4
2004/7
Ver. 1.1
MDT10C23
(1)IAR ( Indirect Address Register) : R0 (2) RTCC (Real Time Counter/Counter Register) : R1 (2) PC (Program Counter) : R2 Write PC, CALL --- always 0 LJUMP, JUMP, LCALL --- from instruction word RTIW, RET --- from STACK
A10
A9
A8
A7~A0
Write PC, JUMP, CALL --- from STATUS B6 b5 LJUMP, LCALL --- from instruction word RTIW, RET --- from STACK
Write PC --- from ALU LJUMP, JUMP, LCALL, CALL --- from instruction word RTIW, RET --- from STACK (4) STATUS (Status register) : R3 Bit 0 1 2 3 4 6-5 Symbol C HC Z PF TF page Carry bit Half Carry bit Zero bit Power loss Flag bit Time overflow Flag bit ROM Page select bit : 00 : 000H --- 1FFH 01 : 200H --- 3FFH 10 : 400H --- 5FFH 11 : 600H --- 7FFH 7 XX General purpose bit Function
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 5
2004/7
Ver. 1.1
MDT10C23
(5) MSR (Memory Select Register) : R4 Memory Select Register : 00 : 10~1F 01 : 30~3F 10 : 50~5F 11 : 70~7F
b7
b6
b5
b4
b3
b2
b1
b0
Read only "1" Indirect Addressing Mode (6) PORT A : R5 PA7~PA0, I/O Register for 22, 24 pins PA5~PA0, I/O Register for 20 pins PA3~PA0, I/O Register for 18 pins (7) PORT B : R6 PB7~PB0, I/O Register (8) CMR(Comparator Mode Register) : R7 Bit 0 Function 0: Define PA0 as TTL input 1: Define PA0 as comparator input 1 0: Define PA1 as TTL input 1: Define PA1 as comparator input 2 0: Define PA2 as TTL input 1: Define PA2 as comparator input 3 0: Define PA3 as TTL input 1: Define PA3 as comparator input 5:4 Reference Voltage select 00: 1/4 VDD 01: 1/2 VDD 10: 3/4 VDD 11: VREF (External pin and PA4 must be set to input) 7:6 Register bits
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 6
2004/7
Ver. 1.1
MDT10C23
(9) TMR (Time Mode Register) Bit Symbol Prescaler Value 00 0 001 010 011 2X0 PS2X0 100 101 110 Function RTCC rate 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 WDT rate 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64
3
PSC
4
TCE
5
TCS
111 1 : 256 1 : 128 Prescaler assignment bit : 0 X RTCC 1 X Watchdog Timer RTCC signal Edge : 0 X Increment on low-to-high transition on RTCC pin 1 X Increment on high-to-low transition on RTCC pin RTCC signal set : 0 X Internal instruction cycle clock 1 X Transition on RTCC pin
(10) CPIO A, CPIO B (Control Port I/O Mode Register) The CPIO register is "write-only" x"0", I/O pin in output mode; x"1", I/O pin in input mode. (11) ROM Option by writer programming :
Oscillator Type RC Oscillator
Oscillator Start-up Time 150 s 20 ms 40 ms 80 ms
LFXT Oscillator XTAL Oscillator HFXT Oscillator
Watchdog Timer control Watchdog timer disable all the time Watchdog timer enable all the time
Power Edge Detect PED Disable PED Enable
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 7
2004/7
Ver. 1.1
MDT10C23
(B) Program Memory
Address 000- 7FF 7FF Program memory
Description
The starting address of the power on, external reset or WDT
8. Reset Condition for all Registers
Register CPIO A CPIO B TMR IAR RTCC PC STATUS MSR PORT A PORT B CMR Address 00h 01h 02h 03h 04h 05h 06h 07h Power-On Reset 1111 1111 1111 1111 --11 1111 xxxx xxxx 1111 1111 0001 1xxx 100x xxxx xxxx xxxx xxxx xxxx 0000 0000 /MCLR Reset 1111 1111 1111 1111 --11 1111 uuuu uuuu 1111 1111 000# #uuu 100u uuuu uuuuuuuu uuuu uuuu uuuu uuuu WDT Reset 1111 1111 1111 1111 --11 1111 uuuu uuuu 1111 1111 000# #uuu 1uuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
Note : uxunchanged, xxunknown, - xunimplemented, read as "0" #xvalue depends on the condition of the following table
Condition /MCLR reset (not during SLEEP) /MCLR reset during SLEEP WDT reset (not during SLEEP) WDT reset during SLEEP
Status: bit 4 U 1 0 0
Status: bit 3 u 0 1 0
9. Instruction Set
Instruction Code 010000 00000000 010000 00000001 010000 00000010 Mnemonic Operands NOP CLRWT SLEEP Function No operation Clear Watchdog timer Sleep mode Operating None 0/WT 0/WT, stop OSC TF, PF TF, PF Status
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P. 8
2004/7
Ver. 1.1
MDT10C23
Instruction Code 010000 00000011 010000 00000100 010000 00000rrr 010001 1rrrrrrr 011000 trrrrrrr 111010 iiiiiiii 010111 trrrrrrr 011001 trrrrrrr 011010 trrrrrrr 011011 trrrrrrr 011100 trrrrrrr 011101 trrrrrrr 011110 trrrrrrr 010010 trrrrrrr 110100 iiiiiiii 010011 trrrrrrr 110101 iiiiiiii 010100 trrrrrrr 110110 iiiiiiii 011111 trrrrrrr 010110 trrrrrrr 010101 trrrrrrr 010000 1xxxxxxx 010001 0rrrrrrr 0000bb brrrrrrr 0010bb brrrrrrr 0001bb brrrrrrr 0011bb brrrrrrr 100nnn nnnnnnnn 101nnn nnnnnnnn 110000 nnnnnnnn 110001 iiiiiiii 11001n nnnnnnnn Mnemonic Operands TMODE RET CPIO R STWR R LDR R, t LDWI I SWAPR R, t INCR R, t INCRSZ R, t ADDWR R, t SUBWR R, t DECR R, t DECRSZ R, t ANDWR R, t ANDWI i IORWR R, t IORWI i XORWR R, t XORWI i COMR R, t RRR RLR CLRW CLRR BCR BSR R R, b R, b R, t R, t Function Load W to TMODE register Return Control I/O port register Store W to register Load register Load immediate to W Swap halves register Increment register Increment register, skip if zero Add W and register Subtract W from register Decrement register Decrement register, skip if zero AND W and register AND W and immediate Inclu. OR W and register Inclu. OR W and immediate Exclu. OR W and register Exclu. OR W and immediate Complement register Rotate right register Rotate left register Clear working register Clear register Bit clear Bit set Bit Test, skip if clear Bit Test, skip if set Long CALL subroutine Long JUMP to address Call subroutine Return, place immediate to W n JUMP to address Operating W/TMODE Stack/PC W/CPIO r W/R R/t I/W [R(0~3)R(4~7)]/t R + 1/t R + 1/t W + R/t R W/t (R+/W+1/ t) R 1/t R 1/t R a W/t i a W/W R a W/t i a W/W R o W/t i o W/W /R/t R(n) /R(n-1), C/ R(7), R(0)/C R(n)/r(n+1), C/R(0), R(7)/C 0/W 0/R 0/R(b) 1/R(b) Skip if R(b)=0 Skip if R(b)=1 n/PC, PC+1/Stack n/PC n/PC, PC+1/Stack Stack/PC,i/W n/PC Z Z None None None None None None None None None Status None None None None Z None None Z None C, HC, Z C, HC, Z Z None Z Z Z Z Z Z Z C C
BTSC R, b BTSS R, b LCALL n LJUMP n CALL RTIW JUMP n i
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 9
2004/7
Ver. 1.1
MDT10C23
Note : W WT TMODE CPIO TF PF PC OSC Inclu. Exclu. AND : : : : : : : : : : : Working register Watchdog timer TMODE mode register Control I/O port register Timer overflow flag Power loss flag Program Counter Oscillator Inclusive `a' Exclusive `o' Logic AND `a' b t : : 0 1 : : : : : : : : Bit position Target : Working register : General register General register address Carry flag Half carry Zero flag Complement Don't care Immediate data ( 8 bits ) Immediate address
R C HC Z / x i n
10. Electrical Characteristics
(Operating temperature at 25J). Sym Description Condition Min 2.3 Typ Max 6.3 Unit V
Vdd Operating voltage VIL Input Low Voltage PA, PB RTCC, /MCLR VIH Input high Voltage PA, PB RTCC, /MCLR IIL VOL Input leakage current Output Low Voltage PA, PB Vdd=5V, IOL=20mA Vdd=5V, IOL=5mA VOH Output High Voltage PA, PB Vdd=5V, IOH= -20mA Vdd=5V, IOH= -5mA Islp Islp Sleep current (WDT disable) Sleep current (WDT enable) Vddx 2.3 ~ 6.3 V Vddx 2.3 V Vddx 3.0 V Vddx 4.0 V Vddx 5.0 V Vddx 6.3 V Vpr Power Edge-detector Reset Voltage Vddx 2.3 V Vddx 3.0 V Vddx 4.0 V Vddx 5.0 V Vddx 6.3 V Vdd=5V Vdd=5V Vdd=5V Vdd=5V Vdd=5V
-0.6 -0.6
1.0 1.0
V V
2.0 3.2
Vdd Vdd +/-1
V V A
0.4 0.1
V V
3.8 4.5 0.1 1 15 5 9 20 1.1 32.8 27.2 22.8 20.3 17.8 1.3 1.0
V V A A A A A A V mS mS mS mS mS
Twdt The basic WDT time-out cycle time
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 10
2004/7
Ver. 1.1
MDT10C23
Sym TFLT /MCLR filter Icc Comparator Supply current (one comparator) Vref Input reference voltage Comparator Response time V-=Vdd/4, V+=V- 0.2v --V-=Vdd/2, V+=V- 0.2v V-=Vdd3/4, V+=V- 0.2v V-=VDD-0.8,V+=V 0.2v Vdd=2.5v ~6.3v Vdd=5.0v , V- = Vref V+ = (PA0~PA3) 8 8 8 8 S S S S Vdd-0.8v V Description Condition Vddx 5.0 V Vdd=5.0v Min Typ 600 15 Max Unit nS A
11. Operating Current
Temperaturex25 J, the typical value as followings : 11.1 OSC TypexRC ; WDTEnable; Comparator Disable @ Vddx 5.0 V
Cext. (F)
Rext. (Ohm) 4.7 K 10.0 K
Frequency (Hz) 11.4M 6.44 M 1.53 M 732 K 250.8 K 155.6 K 5.6 M 2.89 M 654.4 K 306.8 K 104.4 K 65.2 K 748K 367K 80K 38K 12.8K 8K
Current (A) 1.3 mA 750 A 210 A 120 A 60 A 50 A 660 A 360 A 110 A 70 A 45 A 40 A 200 A 155 A 115 A 110 A 105 A 100 A
3P
47.0 K 100.0 K 300.0 K 470.0 K 4.7 K 10.0 K
20P
47.0 K 100.0 K 300.0 K 470.0 K 4.7 K 10.0 K
300P
47.0 K 100.0 K 300.0 K 470.0 K
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 11
2004/7
Ver. 1.1
MDT10C23
11.2 OSC TypexLF (C=20 p); WDTDisable ; Comparator Disable Voltage/Frequency 2.3 V 3.0 V 4.0 V 5.0 V 6.3 V 32 K 3 A 4 A 8 A 12 A 25 A 455 K X 40 A 65 A 90 A 120 A
@3.5v
1M
Sleep O0.1 A
75 A
O0.1 A O0.1 A O0.1 A O0.1 A
100 A 150 A 210 A
11.3 OSC TypexXT (C=10 p); WDTEnable ; Comparator Disable Voltage/Frequency 2.1 V 3.0 V 4.0 V 5.0 V 6.3 V 1M 60 A 100 A 200 A 400 A 600 A 4M 180 A 280 A 450 A 650 A 900 A 10 M 450 A 700 A 1.0 mA 1.2 mA 1.8 mA Sleep O0.1 A 1.5 A 4.0 A 8.0 A 18.0 A
11.4 OSC TypexHF (C=10 p); WDTEnable ; Comparator Disable Voltage/Frequency 2.1 V 3.0 V 4.0 V 5.0 V 6.3 V 4M 165 A 320 A 550 A 700 A 1.0 mA 10 M 400 A 700 A 1.0mA 1.4 mA 2.0 mA 20 M
@2.3v
Sleep O0.1 A 1.5 A 4 A 8 A 18 A
850 A
1.2 mA 1.9 mA 2.6 mA 3.5 mA
11.5 Power Edge-detector Reset Voltage (Not in Sleep Mode), @ Vddx 5.0 V Vpr O 1.6~1.7 V Vpr
R
Vdd (Power Supply)
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P. 12
2004/7
Ver. 1.1
MDT10C23
12. Port A Equivalent Circuit
PA0-PA3
D I/O Control Latch
Q
I/O Control
C K
Q B
D Data O/P Latch G QB
Port I/O Pin
Write
Input Resistor
Data Bus QB Rea d Data I/P Latch G D S
0 TTL input level
1
+ comparator level VREF
Compartor Control
PA4
D I/O Control Latch Q
I/O Control
C K
Q B
D Data O/P Latch G Q B Input Resistor Data Bus Rea d QB Data I/P Latch G D TTL Input Level
Port I/O Pin
Write
comparator enable
3 2 Vref 1 S0 S1 0 CMR_4 CMR_5
3/4 VDD 1/2 VDD 1/4 VDD
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 13
2004/7
Ver. 1.1
MDT10C23
PA5-PA7
D I/O Control Latch
Q
I/O Control
C K
Q B
D Data O/P Latch G Q B
Port I/O Pin
Write
Data Bus Rea d
QB Data I/P Latch
D Input Resistor TTL Input Level
G
Port B Equivalent Circuit
D I/O Control Latch
Q
I/O Control
C K
Q B
Port I/O Pin D Data O/P Latch G Q B
Write
Data Bus Rea d
QB Data I/P Latch G
D Input Resistor TTL Input Level
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 14
2004/7
Ver. 1.1
MDT10C23
13. MCLRB and RTCC Input Equivalent Circuit
MOS Pull Hi (Long Channel)
R U 1 K
MCLRB Schmitt Trigger
Information Sheet Pull Hi/Lo Selection
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 15
2004/7
Ver. 1.1
MDT10C23
MOS Pull Hi (Long Channel)
R U 1 K
RTCC Schmitt Trigger
MOS Pull Low (Long Channel)
Information Sheet Pull Hi/Lo Selection
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 16
2004/7
Ver. 1.1
MDT10C23
13. Capacitor Selection For Crystal Oscillator (a) With built-in Oscillation Capacitors ( Default for HF,XT,LF ) @ Vddx 2.3V~5.5 V , C1=C2=10P~15P
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 17
2004/7
Ver. 1.1
MDT10C23
(b) Without built-in Oscillation Capacitors @ Vddx 3.0 V~ 5.0 V Osc. Type Resonator Freq. 20 MHz HF 10 MHz 4 MHz 10 MHz XT 4 MHz 1 MHz 1 MHz LF 455 K 32 K C1 5 pF ~10 pF 10 pF ~50 pF 10 pF ~50 pF 10 pF ~30 pF 10 pF ~50 pF 10 pF ~30 pF 3 pF ~5 pF 10 pF ~30 pF 10 pF ~20 pF C2 10 pF~30 pF 20 pF ~100 pF 20 pF ~100 pF 10 pF ~50 pF 20 pF ~100 pF 20 pF ~50 pF 3 pF ~5 pF 20 pF ~50 pF 15 pF ~30 pF
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 18
2004/7
Ver. 1.1
MDT10C23
To increase the stability of oscillator and the ability of anti-noise, the above values of the external capacitor range are recommended, but the higher capacitance will increase the start-up time. There do not have built-in Oscillation Capacitors for RC type.
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 19
2004/7
Ver. 1.1

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